In these years, the resolution of a digital image display device such as LCD (liquid crystal display) or PDP (plasma display panel) has been improved in recent years. The operating speed of an LSI (large scale integration) for converting an analog image signal to a digital image signal has correspondingly been increased. For operating an LSI at a high speed, the circuit is usually designed to use finer transistors having a smaller stray capacitance and a higher current driving force. With respect to a part of the LSI which cannot be easily made operate at a high-speed, a technique for operating a plurality of circuits having the identical function in parallel is employed to obtain substantial high-speed operation.
Even in an imaging ADC for supplying a digital image signal to a digital image display device, as in the above case, an advanced processing technology is used to widen a bandwidth, and the parallel operation based on interleave operation is used. However, there are variations in characteristics among a plurality of ADCs for performing parallel operation due to the limitation of a micro-machining technology. This results in deteriorated characteristics, for example, generation of a differential linearity error or an integral linearity error.
FIG. 12 shows an exemplary configuration of a prior art imaging ADC. The imaging ADC 110 has first to N-th ADCs 111 for performing parallel operation, a multi-phase clock signal generating circuit 112 for supplying multi-phase clock signals to the ADCs 111, and a selector circuit 113 for selecting one of output signals of the ADCs 111. The first to N-th ADCs 111 sequentially convert an analog signal to a digital signal in synchronism with the multi-phase clock signals received from the multi-phase clock signal generating circuit 112. In this example, reference symbol N denotes a degree of parallelism of the ADCs.
In general, in an image signal, as shown in FIG. 13, pixel information corresponding to one line continues from the upper left of the screen to the horizontal direction, and then under the line by one pixel in the vertical direction, pixel information corresponding to another line also continues from the left side of the screen to the horizontal direction. The repetition of the above-mentioned pixel information forms an image signal corresponding to one frame. A number of pixels in one frame, that is, a sampling number of times M in one frame can be obtained from a product of a number of pixels in one line and a number of lines in one frame.
Assume that the sampling number of times M in one frame is divisible by the degree N of parallelism of ADCs, and that the first ADC samples a pixel P (I, 1), the second ADC samples a pixel P (I, 2), and the N-th ADC samples a pixel P (I, N) in a frame (I). Then, even in a frame (I+1), the first ADC samples a pixel P (I+1, 1), the second ADC samples a pixel P (I+1, 2), and the N-th ADC samples a pixel P (I+1, N), in a similar manner. In this case, P (I, J) denotes a J-th pixel in an I-th frame. In such a case, if the first to N-th ADCs vary in characteristics, even when an identical analog signal is inputted to the ADCs, a constant pattern of error occurs in an output digital signal, which results in appearance of irregularities on the display screen.
For the purpose of suppressing the influences of variations in circuit elements including a resistor and a capacitor upon analog/digital conversion characteristics during conversion from an analog image signal to a digital image signal by using a single ADC, output results of the ADC are averaged by sequentially switching (swapping) between a plurality of circuit elements. Even in such a case, with respect to pixels for a plurality of successive frames, if a plurality of circuit elements in the ADC are arranged in the same cycle or sequence, irregularities appear on the screen.
For the purpose of reducing irregularities on the screen caused by such variations, it is also considered to digitally correct the output signal of the imaging ADC. However, such digital correction requires complicated circuit and processing.